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/* ****************************************************************************
 * SuperH assembly-related utilities, user mode.
 * Copyright (C) 2017 Thomas "Cakeisalie5" Touhey <thomas@touhey.fr>
 * ************************************************************************* */
#include <cdefs.h>
#include <stdint.h>
#include <builtin.h>
#include <fixed.h>
__BEGIN_DECLS

/* ************************************************************************* */
/*  SPC interaction                                                          */
/* ************************************************************************* */
/* Here are the intrinsic functions to interact with the saved program
 * counter (SPC), which is basically what is used by the `rts` and `jsr`-like
 * instructions. */

#if __GNUC_ASM
static __inline __uint32_t __get_spc(void) {
	__uint32_t __ret; __asm("ldc.l spc, %0" :: "=r"(__ret)); return (__ret); }
static __inline void     __set_spc(__uint32_t __spc) {
	__asm("stc %0, sr" :: "r"(__spc)); }

# define set_spc(_SPC) __set_spc(_SPC)
# define get_spc()     __get_spc()
#else
extern __uint32_t __asm_get_spc OF((void));
extern void       __asm_set_spc OF((__uint32_t __spc));

# define set_spc(_SPC) __asm_set_spc(_SPC)
# define get_spc()     __asm_get_spc()
#endif
/* ************************************************************************* */
/*  GBR interaction                                                          */
/* ************************************************************************* */
/* The global base register is a register. TODO */

#if __RENESAS_PREREQ(1, 0)
# define set_gbr(_BASE) _builtin_set_gbr(_BASE)
# define get_gbr()      _builtin_get_gbr()

#elif __GNUC_ASM
static __asm_inline __uint32_t __get_gbr(void) {
	__uint32_t __gbr; __asm("ldc.l gbr, %0":"=r"(__gbr):); return (__gbr); }
static __asm_inline void __set_gbr(__uint32_t __gbr) {
	__asm("stc.l %0, gbr"::"r"(__gbr)); }

# define set_gbr(_BASE) __set_gbr(_BASE)
# define get_gbr()      __get_gbr()
#endif
/* ************************************************************************* */
/*  Read and write using the GBR                                             */
/* ************************************************************************* */
/* Here are inline functions to read using the GBR. */

#if __RENESAS_PREREQ(1, 0)
# define gbr_read_byte(_OFF) _builtin_gbr_read_byte(_OFF)
# define gbr_read_word(_OFF) _builtin_gbr_read_word(_OFF)
# define gbr_read_long(_OFF) _builtin_gbr_read_long(_OFF)
# define gbr_write_byte(_OFF, _DATA) _builtin_gbr_write_byte(_OFF, _DATA)
# define gbr_write_word(_OFF, _DATA) _builtin_gbr_write_word(_OFF, _DATA)
# define gbr_write_long(_OFF, _DATA) _builtin_gbr_write_long(_OFF, _DATA)
# define gbr_and_byte(_OFF, _MASK) _builtin_gbr_and_byte(_OFF, _MASK)
# define  gbr_or_byte(_OFF, _MASK)  _builtin_gbr_or_byte(_OFF, _MASK)
# define gbr_xor_byte(_OFF, _MASK) _builtin_gbr_xor_byte(_OFF, _MASK)
# define gbr_tst_byte(_OFF, _MASK) _builtin_gbr_tst_byte(_OFF, _MASK)

#elif __GNUC_ASM
# define gbr_read_byte(_OFF) ({__asm_inline \
  uint8_t __fn__(void) { \
	uint8_t  __ret; __asm("mov.b @(%1, gbr), %0":"=r"(__ret):"I"(_OFF)); \
	return (__ret); } __fn__; })()
# define gbr_read_word(_OFF) ({__asm_inline \
  uint16_t __fn__(void) { \
	uint16_t __ret; __asm("mov.w @(%1, gbr), %0":"=r"(__ret):"I"(_OFF)); \
	return (__ret); } __fn__; })()
# define gbr_read_long(_OFF) ({__asm_inline \
  uint32_t __fn__(void) { \
	uint32_t __ret; __asm("mov.l @(%1, gbr), %0":"=r"(__ret):"I"(_OFF)); \
	return (__ret); } __fn__; })()

# define gbr_write_byte(_OFF, _DATA) \
	__asm("mov.b %0, @(%1, gbr)" :: "r"(_DATA), "G"(_OFF));
# define gbr_write_word(_OFF, _DATA) \
	__asm("mov.w %0, @(%1, gbr)" :: "r"(_DATA), "I"(_OFF));
# define gbr_write_long(_OFF, _DATA) \
	__asm("mov.l %0, @(%1, gbr)" :: "r"(_DATA), "I"(_OFF));

# define gbr_and_byte(_OFF, _MASK) \
	__asm("and.b %0, @(%1, gbr)" :: "r"(_MASK), "I"(_OFF));
# define  gbr_or_byte(_OFF, _MASK) \
	__asm("or.b %0, @(%1, gbr)"  :: "r"(_MASK), "I"(_OFF));
# define gbr_xor_byte(_OFF, _MASK) \
	__asm("xor.b %0, @(%1, gbr)" :: "r"(_MASK), "I"(_OFF));
# define gbr_tst_byte(_OFF, _MASK) \
	__asm("tst.b %0, @(%1, gbr)" :: "r"(_MASK), "I"(_OFF));
#endif
/* ************************************************************************* */
/*  Test and set instruction                                                 */
/* ************************************************************************* */
/* This instruction purges the cache block corresponding to a memory area.
 * Here is the macro: */

#if __RENESAS_PREREQ(1, 0)
# define tas(_ADDR) _builtin_tas(_ADDR)
#elif __GNUC_ASM
# define tas(_ADDR) __asm("tas.b @%0"::"r"(_ADDR))
#endif
/* ************************************************************************* */
/*  Trap Always                                                              */
/* ************************************************************************* */
/* This instruction goes to the exception handler with privileged mode.
 * It can be useful for syscalls: */

#if __RENESAS_PREREQ(1, 0)
# define trapa(_NO) _builtin_trapa(_NO)
#elif __GNUC_ASM
# define trapa(_NO) __asm("trapa #%0"::"r"(_NO))
#endif
/* ************************************************************************* */
/*  Multiply and Accumulate                                                  */
/* ************************************************************************* */
/* This instruction performs signed multiplication of two operands. */

#if defined(_SH1)
#elif __RENESAS_PREREQ(1, 0)
# define macw(_PTR1, _PTR2, _COUNT) \
	_builtin_macw(_PTR1, _PTR2, _COUNT)
# define macwl(_PTR1, _PTR2, _COUNT, _MASK) \
	_builtin_macwl(_PTR1, _PTR2, _COUNT, _MASK)
# define macl(_PTR1, _PTR2, _COUNT) \
	_builtin_macl(_PTR1, _PTR2, _COUNT)
# define macll(_PTR1, _PTR2, _COUNT, _MASK) \
	_builtin_macll(_PTR1, _PTR2, _COUNT, _MASK)

#elif __GNUC_ASM
# define macw(_PTR1, _PTR2, _COUNT) ({__asm_inline \
  uint32_t __fn__(uint16_t *__p1, uint16_t *__p2) { \
	uint32_t __macl, __mach; \
	__asm("sts macl, %0\r\n" "sts mach, %1":"=r"(__macl), "=r"(__mach)); \
	__asm("clrmac"); \
	int __count; for (__count = 0; __count < (_COUNT); __count++) \
		__asm("mac.w @%0+, @%1+"::"r"(__p1), "r"(__p2)); \
	uint32_t __mul; __asm("sts macl, %0":"=r"(__mul)); \
	__asm("lds %0, macl"::"r"(__macl)); \
	__asm("lds %0, mach"::"r"(__mach)); \
	return (__mul); } __fn__; })(_PTR1, _PTR2)
# define macwl(_PTR1, _PTR2, _COUNT, _MASK) ({__asm_inline \
  uint32_t __fn__(uint16_t *__p1, uint16_t *__p1, uint16_t __mask) { \
	uint32_t __macl, __mach; \
	__asm("sts macl, %0\r\n" "sts mach, %1":"=r"(__macl), "=r"(__mach)); \
	__asm("clrmac"); \
	int __count; for (__count = 0; __count < (_COUNT); __count++) \
		__asm("mac.w @%0+, @%1+\r\n" "and %2, %1" \
			::"r"(__p1), "r"(__p2), "r"(__mask)); \
	uint32_t __mul; __asm("sts macl, %0":"=r"(__mul)); \
	__asm("lds %0, macl"::"r"(__macl)); \
	__asm("lds %0, mach"::"r"(__mach)); \
	return (__mul); } __fn__; })(_PTR1, _PTR2, _MASK)

# define macl(_PTR1, _PTR2, _COUNT) ({__asm_inline \
  uint32_t __fn__(uint32_t *__p1, uint32_t *__p2) { \
	uint32_t __macl, __mach; \
	__asm("sts macl, %0\r\n" "sts mach, %1":"=r"(__macl), "=r"(__mach)); \
	__asm("clrmac"); \
	int __count; for (__count = 0; __count < (_COUNT); __count++) \
		__asm("mac.l @%0+, @%1+"::"r"(__p1), "r"(__p2)); \
	uint32_t __mul; __asm("sts macl, %0":"=r"(__mul)); \
	__asm("lds %0, macl"::"r"(__macl)); \
	__asm("lds %0, mach"::"r"(__mach)); \
	return (__mul); } __fn__; })(_PTR1, _PTR2)
# define macll(_PTR1, _PTR2, _COUNT, _MASK) ({__asm_inline \
  uint32_t __fn__(uint32_t *__p1, uint32_t *__p1, uint32_t __mask) { \
	uint32_t __macl, __mach; \
	__asm("sts macl, %0\r\n" "sts mach, %1":"=r"(__macl), "=r"(__mach)); \
	__asm("clrmac"); \
	int __count; for (__count = 0; __count < (_COUNT); __count++) \
		__asm("mac.l @%0+, @%1+\r\n" "and %2, %1" \
			::"r"(__p1), "r"(__p2), "r"(__mask)); \
	uint32_t __mul; __asm("sts macl, %0":"=r"(__mul)); \
	__asm("lds %0, macl"::"r"(__macl)); \
	__asm("lds %0, mach"::"r"(__mach)); \
	return (__mul); } __fn__; })(_PTR1, _PTR2, _MASK)
#endif
/* ************************************************************************* */
/*  OS System Call                                                           */
/* ************************************************************************* */
/* Notice that CASIOWIN (CASIO's system) doesn't use this interface, so this
 * will not work with it. */

#if __RENESAS_PREREQ(1, 0)
# define trapa_svc _builtin_trapa_svc

#elif __GNUC_ASM && defined(__count_va_args)
/* generators */
# define __make_trapa_svc_1(_CODE, _R0) ({__asm_inline \
  int __fn__(void) { \
	register int __ret asm ("r0")  = (_R0); \
	\
	__asm("trapa %0" :: "i"(_CODE)); \
	return (__ret); } \
	__fn__; })
# define __make_trapa_svc_2(_CODE, _R0, _R4) ({__asm_inline \
  int __fn__(void) { \
	register int __ret  asm ("r0") = (_R0); \
	register int __arg4 asm ("r4") = (_R4); \
	\
	__asm("trapa %0" :: "i"(_CODE)); \
	return (__ret); } \
	__fn__; })
# define __make_trapa_svc_3(_CODE, _R0, _R4, _R5) ({__asm_inline \
  int __fn__(void) { \
	register int __ret  asm ("r0") = (_R0); \
	register int __arg4 asm ("r4") = (_R4); \
	register int __arg5 asm ("r5") = (_R5); \
	\
	__asm("trapa %0" :: "i"(_CODE)); \
	return (__ret); } \
	__fn__; })
# define __make_trapa_svc_4(_CODE, _R0, _R4, _R5, _R6) ({__asm_inline \
  int __fn__(void) { \
	register int __ret  asm ("r0") = (_R0); \
	register int __arg4 asm ("r4") = (_R4); \
	register int __arg5 asm ("r5") = (_R5); \
	register int __arg6 asm ("r6") = (_R6); \
	\
	__asm("trapa %0" :: "i"(_CODE)); \
	return (__ret); } \
	__fn__; })
# define __make_trapa_svc_5(_CODE, _R0, _R4, _R5, _R6, _R7) ({__asm_inline \
  int __fn__(void) { \
	register int __ret  asm ("r0") = (_R0); \
	register int __arg4 asm ("r4") = (_R4); \
	register int __arg5 asm ("r5") = (_R5); \
	register int __arg6 asm ("r6") = (_R6); \
	register int __arg7 asm ("r7") = (_R7); \
	\
	__asm("trapa %0" :: "i"(_CODE)); \
	return (__ret); } \
	__fn__; })

/* clearer warnings (errors made on purpose deserve unreadable errors) */
# define __make_trapa_svc_6(...) \
	_Pragma("GCC error \"trapa_svc takes up to six arguments only\"")
# define __make_trapa_svc_7(...) \
	_Pragma("GCC error \"trapa_svc takes up to six arguments only\"")
# define __make_trapa_svc_8(...) \
	_Pragma("GCC error \"trapa_svc takes up to six arguments only\"")
# define __make_trapa_svc_9(...) \
	_Pragma("GCC error \"trapa_svc takes up to six arguments only\"")
# define __make_trapa_svc_10(...) \
	_Pragma("GCC error \"trapa_svc takes up to six arguments only\"")
# define __make_trapa_svc_11(...) \
	_Pragma("GCC error \"trapa_svc takes up to six arguments only\"")
# define __make_trapa_svc_12(...) \
	_Pragma("GCC error \"trapa_svc takes up to six arguments only\"")

/* main macros */
# define trapa_svc(_CODE, _R0, ...) \
	__trapa_svc_(_CODE, _R0, ##__VA_ARGS__)
# define __trapa_svc_(_CODE, ...) \
	__concat(__make_trapa_svc_, __count_va_args(__VA_ARGS__))\
		(_CODE, __VA_ARGS__)()
#endif
/* ************************************************************************* */
/*  Prefetch Data to the Cache                                               */
/* ************************************************************************* */
/* Load data to cache on software prefetching. */

#if !defined(_SH2A) && !defined(_SH2AFPU) && !defined(_SH3) \
	&& !defined(_SH3DSP) && !defined(_SH4) && !defined(_SH4A) \
	&& !defined(_SH4ALDSP)
#elif __RENESAS_PREREQ(1, 0)
# define prefetch(_X)  _builtin_prefetch(_X)

#elif __GNUC_ASM
static __asm_inline void __prefetch(void *addr) {
	__asm("pref @%0"::"r"(addr)); }

# define prefetch(_X) __prefetch(_X)
#endif
/* ************************************************************************* */
/*  Interact with the FPU System Register                                    */
/* ************************************************************************* */
/* The FPU System Register is <TODO: describe it>. */

#if !defined(_SH2E) && !defined(_SH2AFPU) && !defined(_SH4) \
	&& !defined(_SH4A)
#elif __RENESAS_PREREQ(6, 0)
# define set_fpscr(_CR) _builtin_set_fpscr(_CR)
# define get_fpscr()    _builtin_get_fpscr()

#elif __GNUC_ASM
static __asm_inline void __set_fpscr(__uint32_t __cr) {
	__asm("lds %0, FPSCR"::"r"(__cr)); }
static __asm_inline __uint32_t __get_fpscr(void) {
	__uint32_t __fpscr; __asm("sts FPSCR, %0":"=r"(__fpscr):);
	return (__fpscr); }

# define set_fpscr(_CR) __set_fpscr(_CR)
# define get_fpscr()    __get_fpscr()
#endif
/* ************************************************************************* */
/*  Floating-point Operations                                                */
/* ************************************************************************* */
/* FIPR is Floating-Point Inner Product,
 * FTRV is Floating-Point Transform Vector.
 * MTRX is matrix. */

#if !defined(_SH2AFPU) && !defined(_SH4) && !defined(_SH4A)
#elif __RENESAS_PREREQ(6, 0)
# define add4(_VEC1, _VEC2, _VEC3) _builtin_add4(_VEC1, _VEC2, _VEC3)
# define sub4(_VEC1, _VEC2, _VEC3) _builtin_sub4(_VEC1, _VEC2, _VEC3)

# if !defined(_SH2AFPU)
#  define ld_ext(_MAT) _builtin_ld_ext(_MAT)
#  define st_ext(_MAT) _builtin_st_ext(_MAT)

#  define fipr(_VEC1, _VEC2)           _builtin_fipr(_VEC1, _VEC2)
#  define ftrv(_VEC1, _VEC2)           _builtin_ftrv(_VEC1, _VEC2)
#  define ftrvadd(_VEC1, _VEC2, _VEC3) _builtin_ftrvadd(_VEC1, _VEC2, _VEC3)
#  define ftrvsub(_VEC1, _VEC2, _VEC3) _builtin_ftrvsub(_VEC1, _VEC2, _VEC3)

#  define mtrx4mul(_MAT1, _MAT2) _builtin_mtrx4mul(_MAT1, _MAT2)
#  define mtrx4muladd(_MAT1, _MAT2, _MAT3) \
	_builtin_mtrx4muladd(_MAT1, _MAT2, _MAT3)
#  define mtrx4mulsub(_MAT1, _MAT2, _MAT3) \
	_builtin_mtrx4mulsub(_MAT1, _MAT2, _MAT3)
# endif

#elif __GNUC_ASM
static __asm_inline void __add4(float __vec1[4], float __vec2[4],
  float __vec3[4]) {
	__asm("fmov.s @%0+, fr0\r\n"
		"fmov.s @%0+, fr1\r\n"
		"fmov.s @%0+, fr2\r\n"
		"fmov.s @%0+, fr3\r\n"
		"fmov.s @%1+, fr4\r\n"
		"fadd    fr4, fr0\r\n"
		"fmov.s @%1+, fr5\r\n"
		"fadd    fr5, fr1\r\n"
		"fmov.s @%1+, fr6\r\n"
		"fadd    fr6, fr2\r\n"
		"fmov.s @%1+, fr7\r\n"
		"fadd    fr7, fr3\r\n"
		"fmov.s fr3, @-%2\r\n"
		"fmov.s fr2, @-%2\r\n"
		"fmov.s fr1, @-%2\r\n"
		"fmov.s fr0, @-%2\r\n"
		:: "r"(__vec1), "r"(__vec2), "r"(&__vec3[4])); }
static __asm_inline void __sub4(float __vec1[4], float __vec2[4],
  float __vec3[4]) {
	__asm("fmov.s @%0+, fr0\r\n"
		"fmov.s @%0+, fr1\r\n"
		"fmov.s @%0+, fr2\r\n"
		"fmov.s @%0+, fr3\r\n"
		"fmov.s @%1+, fr4\r\n"
		"fsub    fr4, fr0\r\n"
		"fmov.s @%1+, fr5\r\n"
		"fsub    fr5, fr1\r\n"
		"fmov.s @%1+, fr6\r\n"
		"fsub    fr6, fr2\r\n"
		"fmov.s @%1+, fr7\r\n"
		"fsub    fr7, fr3\r\n"
		"fmov.s fr3, @-%2\r\n"
		"fmov.s fr2, @-%2\r\n"
		"fmov.s fr1, @-%2\r\n"
		"fmov.s fr0, @-%2\r\n"
		:: "r"(__vec1), "r"(__vec2), "r"(&__vec3[4])); }
static __asm_inline void __ld_ext(float __vec[4][4]) {
	__asm("frchg\r\n"
		"fmov.s @%0+, fr0 \r\n"
		"fmov.s @%0+, fr1 \r\n"
		"fmov.s @%0+, fr2 \r\n"
		"fmov.s @%0+, fr3 \r\n"
		"fmov.s @%1+, fr4 \r\n"
		"fmov.s @%1+, fr5 \r\n"
		"fmov.s @%1+, fr6 \r\n"
		"fmov.s @%1+, fr7 \r\n"
		"fmov.s @%2+, fr8 \r\n"
		"fmov.s @%2+, fr9 \r\n"
		"fmov.s @%2+, fr10\r\n"
		"fmov.s @%2+, fr11\r\n"
		"fmov.s @%3+, fr12\r\n"
		"fmov.s @%3+, fr13\r\n"
		"fmov.s @%3+, fr14\r\n"
		"fmov.s @%3+, fr15\r\n"
		"frchg"
		:: "r"(__vec[0]), "r"(__vec[1]), "r"(__vec[2]), "r"(__vec[3])); }
static __asm_inline void __st_ext(float __vec[4][4]) {
	__asm("frchg\r\n"
		"fmov.s fr15, @-%3\r\n"
		"fmov.s fr14, @-%3\r\n"
		"fmov.s fr13, @-%3\r\n"
		"fmov.s fr12, @-%3\r\n"
		"fmov.s fr11, @-%2\r\n"
		"fmov.s fr10, @-%2\r\n"
		"fmov.s fr9 , @-%2\r\n"
		"fmov.s fr8 , @-%2\r\n"
		"fmov.s fr7 , @-%1\r\n"
		"fmov.s fr6 , @-%1\r\n"
		"fmov.s fr5 , @-%1\r\n"
		"fmov.s fr4 , @-%1\r\n"
		"fmov.s fr3 , @-%0\r\n"
		"fmov.s fr2 , @-%0\r\n"
		"fmov.s fr1 , @-%0\r\n"
		"fmov.s fr0 , @-%0\r\n"
		"frchg"
		:: "r"(&__vec[0][4]), "r"(&__vec[1][4]), "r"(&__vec[2][4]),
		   "r"(&__vec[3][4])); }
static __asm_inline void __fipr(float __vec1[4], float __vec2[4]) {
	__asm("fmov.s @%0+, fr0\r\n"
		"fmov.s @%0+, fr1\r\n"
		"fmov.s @%0+, fr2\r\n"
		"fmov.s @%0+, fr3\r\n"
		"fmov.s @%1+, fr4\r\n"
		"fmov.s @%1+, fr5\r\n"
		"fmov.s @%1+, fr6\r\n"
		"fmov.s @%1+, fr7\r\n"
		:: "r"(__vec1), "r"(__vec2)); }
static __asm_inline void __ftrv(float __vec1[4], float __vec2[4]) {
	__asm("fmov.s @%0+, fr0\r\n"
		"fmov.s @%0+, fr1\r\n"
		"fmov.s @%0+, fr2\r\n"
		"fmov.s @%0+, fr3\r\n"
		"ftrv  xmtrx, fv0\r\n"
		"fmov.s fr3, @-%1\r\n"
		"fmov.s fr2, @-%1\r\n"
		"fmov.s fr1, @-%1\r\n"
		"fmov.s fr0, @-%1\r\n"
		:: "r"(__vec1), "r"(&__vec2[4])); }
static __asm_inline void __ftrvadd(float __vec1[4], float __vec2[4],
  float __vec3[4]) {
	__asm("fmov.s @%0+, fr0\r\n"
		"fmov.s @%0+, fr1\r\n"
		"fmov.s @%0+, fr2\r\n"
		"fmov.s @%0+, fr3\r\n"
		"ftrv  xmtrx, fv0\r\n"
		"fmov.s @%1+, fr4\r\n"
		"fmov.s @%1+, fr5\r\n"
		"fmov.s @%1+, fr6\r\n"
		"fadd    fr6, fr2\r\n"
		"fmov.s @%1+, fr7\r\n"
		"fadd    fr5, fr1\r\n"
		"fadd    fr4, fr0\r\n"
		"fadd    fr7, fr3\r\n"
		"fmov.s fr3, @-%2\r\n"
		"fmov.s fr2, @-%2\r\n"
		"fmov.s fr1, @-%2\r\n"
		"fmov.s fr0, @-%2\r\n"
		:: "r"(__vec1), "r"(__vec2), "r"(&__vec3[4])); }
static __asm_inline void __ftrvsub(float __vec1[4], float __vec2[4],
  float __vec3[4]) {
	__asm("fmov.s @%0+, fr0\r\n"
		"fmov.s @%0+, fr1\r\n"
		"fmov.s @%0+, fr2\r\n"
		"fmov.s @%0+, fr3\r\n"
		"ftrv  xmtrx, fv0\r\n"
		"fmov.s @%1+, fr4\r\n"
		"fmov.s @%1+, fr5\r\n"
		"fmov.s @%1+, fr6\r\n"
		"fsub    fr6, fr2\r\n"
		"fmov.s @%1+, fr7\r\n"
		"fsub    fr5, fr1\r\n"
		"fsub    fr4, fr0\r\n"
		"fsub    fr7, fr3\r\n"
		"fmov.s fr3, @-%2\r\n"
		"fmov.s fr2, @-%2\r\n"
		"fmov.s fr1, @-%2\r\n"
		"fmov.s fr0, @-%2\r\n"
		:: "r"(__vec1), "r"(__vec2), "r"(&__vec3[4])); }

static __asm_inline void __mtrx4mul(float __mat1[4][4], float __mat2[4][4]) {
	__ftrv(__mat1[0], __mat2[0]);
	__ftrv(__mat1[1], __mat2[1]);
	__ftrv(__mat1[2], __mat2[2]);
	__ftrv(__mat2[3], __mat2[3]); }
static __asm_inline void __mtrx4muladd(float __mat1[4][4], float __mat2[4][4],
  float __mat3[4][4]) {
	__ftrvadd(__mat1[0], __mat2[0], __mat3[0]);
	__ftrvadd(__mat1[1], __mat2[1], __mat3[1]);
	__ftrvadd(__mat1[2], __mat2[2], __mat3[2]);
	__ftrvadd(__mat1[3], __mat2[3], __mat3[3]); }
static __asm_inline void __mtrx4mulsub(float __mat1[4][4], float __mat2[4][4],
  float __mat3[4][4]) {
	__ftrvsub(__mat1[0], __mat2[0], __mat3[0]);
	__ftrvsub(__mat1[1], __mat2[1], __mat3[1]);
	__ftrvsub(__mat1[2], __mat2[2], __mat3[2]);
	__ftrvsub(__mat1[3], __mat2[3], __mat3[3]); }

# define add4(_VEC1, _VEC2, _VEC3) __add4(_VEC1, _VEC2, _VEC3)
# define sub4(_VEC1, _VEC2, _VEC3) __sub4(_VEC1, _VEC2, _VEC3)

# define ld_ext(_MAT) __ld_ext(_MAT)
# define st_ext(_MAT) __st_ext(_MAT)

# define fipr(_VEC1, _VEC2)           __fipr(_VEC1, _VEC2)
# define ftrv(_VEC1, _VEC2)           __ftrv(_VEC1, _VEC2)
# define ftrvadd(_VEC1, _VEC2, _VEC3) __ftrvadd(_VEC1, _VEC2, _VEC3)
# define ftrvsub(_VEC1, _VEC2, _VEC3) __ftrvsub(_VEC1, _VEC2, _VEC3)

# define mtrx4mul(_MAT1, _MAT2)           __mtrx4mul(_MAT1, _MAT2)
# define mtrx4muladd(_MAT1, _MAT2, _MAT3) __mtrx4muladd(_MAT1, _MAT2, _MAT3)
# define mtrx4mulsub(_MAT1, _MAT2, _MAT3) __mtrx4mulsub(_MAT1, _MAT2, _MAT3)
#endif
/* ************************************************************************* */
/*  Trace a variable on the emulator                                         */
/* ************************************************************************* */
/* Yes, this instruction is specific to the emulator.
 * Why not after all? */

#if defined(_SH1)
#elif __RENESAS_PREREQ(6, 0)
# define trace(_VAR) _builtin_trace(_VAR)
#elif __GNUC_ASM
# define trace(_VAR) __asm("trace %0"::"r"(_VAR))
#endif
/* ************************************************************************* */
/*  Do nothing                                                               */
/* ************************************************************************* */
/* 'nop' stands for 'no operation'.
 * Here is the macro: */

#if __RENESAS_PREREQ(9, 4)
# define nop() _builtin_nop()
#elif __GNUC_ASM
# define nop() __asm("nop")
#endif
/* ************************************************************************* */
/*  Swap bytes                                                               */
/* ************************************************************************* */
/* Swap bytes within words, and words within long words.
 * Here are the inline functions: */

#if __RENESAS_PREREQ(9, 4)
# define swapb(_WORD) _builtin_swapb(_WORD)
# define swapw(_LONG) _builtin_swapw(_LONG)

#elif __GNUC_ASM
static __asm_inline __uint16_t __swapb(__uint16_t __data) {
	__uint16_t __res; __asm("swap.b %1, %0":"=r"(__res):"r"(__data));
	return (__res); }
static __asm_inline __uint32_t __swapw(__uint32_t __data) {
	__uint32_t __res; __asm("swap.w %1, %0":"=r"(__res):"r"(__data));
	return (__res); }

# define swapb(_WORD) __swapb(_WORD)
# define swapw(_LONG) __swapw(_LONG)

#else
# define swapb(_WORD) \
	(((_WORD) & ~0xFFFF) | (((_WORD) & 0xFF00) >> 8) | (((_WORD) & 0xFF) << 8))
# define swapw(_LONG) \
	((((_LONG) & 0xFFFF0000) >> 16) | (((_LONG) & 0xFFFF) << 16))
#endif

/* Here are some other macros that seem to use the last ones...? */

#define end_cnvw(_RM)   swapb(_RM)
#define end_cnvl(_DATA) swapw(_DATA) /* _builtin_end_cnvl(data)? */
/* ************************************************************************* */
/*  Double-length Multiply as Signed                                         */
/* ************************************************************************* */
/* Performs 32-bit multiplication of two operands, and stores the 64-bit
 * result in the MACH and MACL registers.
 * Here are the inline functions: */

#if defined(_SH1)
#elif __RENESAS_PREREQ(9, 4)
# define dmulu_h(_DATA1, _DATA2) _builtin_dmulu_h(_DATA1, _DATA2)
# define dmulu_l(_DATA1, _DATA2) _builtin_dmulu_l(_DATA1, _DATA2)
# define dmuls_h(_DATA1, _DATA2) _builtin_dmuls_h(_DATA1, _DATA2)
# define dmuls_l(_DATA1, _DATA2) _builtin_dmuls_l(_DATA1, _DATA2)

#elif __GNUC_ASM
static __asm_inline __uint32_t __dmulu_h(__uint32_t __data1,
  __uint32_t __data2) {
	__uint32_t __result; __asm("dmulu.l %1, %2\r\n" "lds.l MACH, %0"
		:"=r"(__result) :"r"(__data1), "r"(__data2));
	return (__result); }
static __asm_inline __uint32_t __dmulu_l(__uint32_t __data1,
  __uint32_t __data2) {
	__uint32_t __result; __asm("dmulu.l %1, %2\r\n" "lds.l MACL, %0"
		:"=r"(__result) :"r"(__data1), "r"(__data2));
	return (__result); }
static __asm_inline __int32_t __dmuls_h(__int32_t __data1,
  __int32_t __data2) {
	__int32_t __result; __asm("dmuls.l %1, %2\r\n" "lds.l MACH, %0"
		:"=r"(__result) :"r"(__data1), "r"(__data2));
	return (__result); }
static __asm_inline __int32_t __dmuls_l(__int32_t __data1,
  __int32_t __data2) {
	__int32_t __result; __asm("dmuls.l %1, %2\r\n" "lds.l MACL, %0"
		:"=r"(__result) :"r"(__data1), "r"(__data2));
	return (__result); }

# define dmulu_h(_DATA1, _DATA2) __dmulu_h(_DATA1, _DATA2)
# define dmulu_l(_DATA1, _DATA2) __dmulu_l(_DATA1, _DATA2)
# define dmuls_h(_DATA1, _DATA2) __dmuls_h(_DATA1, _DATA2)
# define dmuls_l(_DATA1, _DATA2) __dmuls_l(_DATA1, _DATA2)
#endif
/* ************************************************************************* */
/*  Floating-Point Sine and Cosine, Square Reciprocal Approximate            */
/* ************************************************************************* */
/* Calculates the sine and cosine, or square reciprocal approximation of FPUL.
 * Here are the macros: */

#if !defined(_SH4A)
#elif __RENESAS_PREREQ(1, 0)
# define fsca(_ANGLE, _SINV, _COSV) _builtin_fsca(_ANGLE, _SINV, _COSV)
# define fsrra(_DATA)               _builtin_fsrra(_DATA)

#elif __GNUC_ASM
static __asm_inline void __fsca(__int32_t __angle, float *__sinv,
  float *__cosv) {
	__asm("lds     %0, fpul\r\n"
		"fsca  fpul,  dr0\r\n"
		"fmov.s fr0,  %1\r\n"
		"fmov.s fr1,  %2\r\n"
		:: "r"(__angle), "mV"(*__sinv), "mV"(*__cosv)); }
static __asm_inline float __fsrra(float __data) {
	float __result = 0;
	__asm("fmov.s @%1, fr9\r\n"
		"fsrra       fr9\r\n"
		"fmov.s fr9, @%0"
		:: "r"(&__result), "r"(&__data));
	return (__result); }

# define fsca(_ANGLE, _SINV, _COSV) __fsca(_ANGLE, _SINV, _COSV)
# define fsrra(_DATA)               __fsrra(_DATA)
#endif
/* ************************************************************************* */
/*  ALU operations (DSP)                                                     */
/* ************************************************************************* */
/* I don't know what these are, but they seem linked. */

#if (!defined(_SH2DSP) && !defined(_SH3DSP) && !defined(_SH4ALDSP)) \
	|| !defined(_DSPC)
#elif __RENESAS_PREREQ(1, 0)
# define pabs_lf(_DATA)  _builtin_pabs_lf(_DATA)
# define pabs_la(_DATA)  _builtin_pabs_la(_DATA)
# define pdmsb_lf(_DATA) _builtin_pdmsb_lf(_DATA)
# define pdmsb_la(_DATA) _builtin_pdmsb_la(_DATA)

# define psha_lf(_DATA, _COUNT) _builtin_psha_lf(_DATA, _COUNT)
# define psha_la(_DATA, _COUNT) _builtin_psha_la(_DATA, _COUNT)

# define long_as_lfixed(_DATA) _builtin_long_as_lfixed(_DATA)
# define lfixed_as_long(_DATA) _builtin_lfixed_as_long(_DATA)

# define rndtoa(_DATA) _builtin_rndtoa(_DATA)
# define rndtof(_DATA) _builtin_rndtof(_DATA)
# define set_cs(_MODE) _builtin_set_cs(_MODE)

#elif __GNUC_ASM
static __asm_inline long __fixed __pabs_lf(long __fixed __data) {
	__asm("movs.l @%0,  y1\r\n"
		"pabs    y1,  x1\r\n"
		"movs.l  x1, @%0"
		:: "r"(&__data));
	return (__data); }
static __asm_inline long __accum __pabs_la(long __accum __data) {
	__asm("movs.l  @%0,  a1 \r\n"
		"movs.l @-%0,  a1g\r\n"
		"pabs     a1,  a0 \r\n"
		"movs.l  a0g, @r2+\r\n"
		"movs.l   a0, @r2"
		:: "r"(&__data));
	return (__data); }
static __asm_inline __fixed __pdmsb_lf(long __fixed __data) {
	__fixed __result = 0;
	__asm("movs.l  @%0,  y1\r\n"
		"pdmsb    y1,  x1\r\n"
		"movs.w   x1, @%1"
		:: "r"(&__data), "r"(&__result));
	return (__result); }
static __asm_inline __fixed __pdmsb_la(long __accum __data) {
	__fixed __result = 0;
	__asm("movs.l  @%0,  a0 \r\n"
		"movs.l @-%0,  a0g\r\n"
		"pdmsb    a0,  x1 \r\n"
		"movs.w   x1, @%1"
		:: "r"(&__data), "r"(&__result));
	return (__result); }

# define pabs_lf(_DATA)         __pabs_lf(_DATA)
# define pabs_la(_DATA)         __pabs_la(_DATA)
# define pdmsb_lf(_DATA)        __pdmsb_lf(_DATA)
# define pdmsb_la(_DATA)        __pdmsb_la(_DATA)

# define psha_lf(_DATA, _COUNT) ({__asm_inline \
int __fn__(long __fixed __data) { \
	__asm("movs.l @%0,  x1\r\n" \
		"psha    %1,  x1\r\n" \
		"movs.l  x1, @%0\r\n" \
		:: "r"(&__data), "i"(_COUNT)); \
	return (__data); }})(_DATA)
# define psha_la(_DATA, _COUNT) ({__asm_inline \
int __fn__(long __accum __data) { \
	__asm("movs.l  @%0,  a1 \r\n" \
		"movs.l @-%0,  a1g\r\n" \
		"psha     %1,  a1 \r\n" \
		"pcopy    a1,  a0 \r\n" \
		"movs.l  a0g, @%0+\r\n" \
		"movs.l   a1, @%0+\r\n" \
		:: "r"(&__data), "i"(_COUNT)); \
	return (__data); }})(_DATA)

static __asm_inline long __fixed __long_as_lfixed(long __data) {
	long __fixed __result;
	__asm("lds    %0,  x1\r\n"
		"movs.l x1, @%1"
		:: "r"(__data), "r"(&__result));
	return (__result); }
static __asm_inline long __lfixed_as_long(long __fixed __data) {
	long __result;
	__asm("movs.l @%1, x1\r\n"
		"sts     x1, %0"
		: "=r"(__result) : "r"(__data));
	return (__result); }

static __asm_inline __accum __rndtoa(long __accum __data) {
	__accum __result = 0;
	__asm("movs.l  @%0,  a0 \r\n"
		"movs.l @-%0,  a0g\r\n"
		"pcopy   a0 ,  x1 \r\n"
		"prnd    x1 ,  x1 \r\n"
		"pcopy   x1 ,  a0 \r\n"
		"movs.w  a0g, @%1+\r\n"
		"movs.w  a0 , @%1"
		:: "r"(&__data), "r"(&__result));
		return (__result); }
static __asm_inline __fixed __rndtof(long __fixed __data) {
	__fixed __result;
	__asm("movs.l @%0,  y1\r\n"
		"prnd    y1,  x1\r\n"
		"movs.w  x1, @%1"
		:: "r"(&__data), "r"(&__result));
	return (__result); }

static __asm_inline uint32_t __get_dsr(void) {
	uint32_t __dsr;
	__asm("sts dsr, %0"
		: "=r"(__dsr));
	return (__dsr); }
static __asm_inline void __set_dsr(uint32_t __dsr) {
	__asm("ldc %0, dsr"
		:: "r"(__dsr)); }

# define long_as_lfixed(_DATA)  __long_as_lfixed(_DATA)
# define lfixed_as_long(_DATA)  __lfixed_as_long(_DATA)
# define rndtoa(_DATA)          __rndtoa(_DATA)
# define rndtof(_DATA)          __rndtof(_DATA)

# define set_cs(_MODE) \
	__set_dsr((__get_dsr() & ~0xE) | (((_MODE) & 0x7) << 1))
#endif
/* ************************************************************************* */
/*  Interact with the Cache                                                  */
/* ************************************************************************* */
/* ICBI and OCBI invalidate the Instruction and Operand Caches.
 * OCBP purges the Operand Cache.
 * OCBWB writes back to the cache.
 * PREFI prefetchs an instruction cache block.
 * SYNCO synchronizes data operations.
 *
 * Here are the macros: */

#if !defined(_SH4A) && !defined(_SH4ALDSP)
#elif __RENESAS_PREREQ(9, 4)
# define icbi(_PTR)     _builtin_icbi(_PTR)
# define ocbi(_PTR)     _builtin_ocbi(_PTR)
# define ocbp(_PTR)     _builtin_ocbp(_PTR)
# define ocbwb(_PTR)    _builtin_ocbwb(_PTR)
# define prefi(_PTR)    _builtin_prefi(_PTR)
# define sleep_i(_SIZE) _builtin_sleep_i(_SIZE)
# define synco()        _builtin_synco()

#elif __GNUC_ASM
# define icbi(_PTR)     __asm("icbi @%0"::"r"(_PTR))
# define ocbi(_PTR)     __asm("ocbi @%0"::"r"(_PTR))
# define ocbp(_PTR)     __asm("ocbp @%0"::"r"(_PTR))
# define ocbwb(_PTR)    __asm("ocbwb @%0"::"r"(_PTR))
# define prefi(_PTR)    __asm("prefi @%0"::"r"(_PTR))
# define sleep_i(_SIZE) __asm("sleep") /* FIXME: no such operation? */
# define synco()        __asm("synco")
#endif
/* ************************************************************************* */
/*  Interact with the T bit                                                  */
/* ************************************************************************* */
/* `movt` gets the T bit, `clrt` sets it to zero, and `sett` sets it to one. */

#if __RENESAS_PREREQ(9, 4)
# define movt() _builtin_movt()
# define clrt() _builtin_clrt()
# define sett() _builtin_sett()

#elif __GNUC_ASM
static __asm_inline int __movt(void) {
	__uint32_t __result; __asm("movt %0":"=r"(__result):);
	return (__result); }

# define movt() __movt()
# define clrt() __asm("clrt")
# define sett() __asm("sett")
#endif
/* ************************************************************************* */
/*  Operations with carry bit management                                     */
/* ************************************************************************* */
/* TODO: explain, because I'm too lazy to do it */

#if __RENESAS_PREREQ(9, 4)
# define xtrct(_DATA1, _DATA2) _builtin_xtrct(_DATA1, _DATA2)
# define addc(_DATA1, _DATA2)  _builtin_addc(_DATA1, _DATA2)
# define addv(_DATA1, _DATA2)  _builtin_addv(_DATA1, _DATA2)
# define subc(_DATA1, _DATA2)  _builtin_subc(_DATA1, _DATA2)
# define subv(_DATA1, _DATA2)  _builtin_subv(_DATA1, _DATA2)
# define negc(_DATA)           _builtin_negc(_DATA)

# define ovf_addc(_DATA1, _DATA2) _builtin_ovf_addc(_DATA1, _DATA2)
# define ovf_addv(_DATA1, _DATA2) _builtin_ovf_addv(_DATA1, _DATA2)
# define unf_subc(_DATA1, _DATA2) _builtin_unf_subc(_DATA1, _DATA2)
# define unf_subv(_DATA1, _DATA2) _builtin_unf_subv(_DATA1, _DATA2)

#elif __GNUC_ASM
static __asm_inline __uint32_t __xtrct(__uint32_t __upper,
  __uint32_t __lower) {
	__asm("xtrct %1, %0"
		: "+r"(__lower) : "r"(__upper));
	return (__lower); }
static __asm_inline __int32_t __addc(__int32_t __data1, __int32_t __data2) {
	__asm("addc %1, %0"
		: "+r"(__data2) : "r"(__data1));
	return (__data2); }
static __asm_inline __int32_t __addv(__int32_t __data1, __int32_t __data2) {
	__asm("addv %1, %0"
		: "+r"(__data2) : "r"(__data1));
	return (__data2); }
static __asm_inline __int32_t __subc(__int32_t __data1, __int32_t __data2) {
	__asm("subc %1, %0"
		: "+r"(__data2) : "r"(__data1));
	return (__data2); }
static __asm_inline __int32_t __subv(__int32_t __data1, __int32_t __data2) {
	__asm("subv %1, %0"
		: "+r"(__data2) : "r"(__data1));
	return (__data2); }
static __asm_inline __int32_t __negc(__int32_t __data) {
	__asm("negc %0, %0" : "+r"(__data));
	return (__data); }

# define xtrct(_UPR, _LWR)     __xtrct(_UPR, _LWR)
# define addc(_DATA1, _DATA2)  __addc(_DATA1, _DATA2)
# define addv(_DATA1, _DATA2)  __addv(_DATA1, _DATA2)
# define subc(_DATA1, _DATA2)  __subc(_DATA1, _DATA2)
# define subv(_DATA1, _DATA2)  __subv(_DATA1, _DATA2)
# define negc(_DATA)           __negc(_DATA)

static __asm_inline int __ovf_addc(__int32_t __data1, __int32_t __data2) {
	__asm("addc %0, %1" :: "r"(__data1), "r"(__data2));
	return (movt()); }
static __asm_inline int __ovf_addv(__int32_t __data1, __int32_t __data2) {
	__asm("addv %0, %1" :: "r"(__data1), "r"(__data2));
	return (movt()); }
static __asm_inline int __unf_subc(__int32_t __data1, __int32_t __data2) {
	__asm("subc %0, %1" :: "r"(__data1), "r"(__data2));
	return (movt()); }
static __asm_inline int __unf_subv(__int32_t __data1, __int32_t __data2) {
	__asm("subv %0, %1" :: "r"(__data1), "r"(__data2));
	return (movt()); }

# define ovf_addc(_DATA1, _DATA2) __ovf_addc(_DATA1, _DATA2)
# define ovf_addv(_DATA1, _DATA2) __ovf_addv(_DATA1, _DATA2)
# define unf_subc(_DATA1, _DATA2) __unf_subc(_DATA1, _DATA2)
# define unf_subv(_DATA1, _DATA2) __unf_subv(_DATA1, _DATA2)
#endif
/* ************************************************************************* */
/*  Division                                                                 */
/* ************************************************************************* */
/* TODO: check the usage of this */

#if __RENESAS_PREREQ(9, 4)
# define div1(_DATA1, _DATA2)  _builtin_div1(_DATA1, _DATA2)
# define div0s(_DATA1, _DATA2) _builtin_div0s(_DATA1, _DATA2)
# define div0u()               _builtin_div0u()

#elif __GNUC_ASM
static __asm_inline __uint32_t __div1(__uint32_t __data1, __uint32_t __data2) {
	__asm("div1 %1, %0"
		: "+r"(__data2) : "r"(__data1));
	return (__data2); }
static __asm_inline __int32_t __div0s(__int32_t __data1, __int32_t __data2) {
	__asm("div0s %0, %1"
		:: "r"(__data1), "r"(__data2));
	return (movt()); }

# define div1(_DATA1, _DATA2)  __div1(_DATA1, _DATA2)
# define div0s(_DATA1, _DATA2) __div0s(_DATA1, _DATA2)
# define div0u()               __asm("div0u")
#endif
/* ************************************************************************* */
/*  Bit rotation                                                             */
/* ************************************************************************* */
/* TODO: check the usage of this */

#if __RENESAS_PREREQ(9, 4)
# define rotl(_DATA)  _builtin_rotl(_DATA)
# define rotr(_DATA)  _builtin_rotr(_DATA)
# define rotcl(_DATA) _builtin_rotcl(_DATA)
# define rotcr(_DATA) _builtin_rotcr(_DATA)

#elif __GNUC_ASM
static __asm_inline __uint32_t __rotl(__uint32_t __data) {
	__asm("rotl %0" : "+r"(__data));
	return (__data); }
static __asm_inline __uint32_t __rotr(__uint32_t __data) {
	__asm("rotr %0" : "+r"(__data));
	return (__data); }
static __asm_inline __uint32_t __rotcl(__uint32_t __data) {
	__asm("rotcl %0" : "+r"(__data));
	return (__data); }
static __asm_inline __uint32_t __rotcr(__uint32_t __data) {
	__asm("rotcr %0" : "+r"(__data));
	return (__data); }

# define rotl(_DATA)  __rotl(_DATA)
# define rotr(_DATA)  __rotr(_DATA)
# define rotcl(_DATA) __rotcl(_DATA)
# define rotcr(_DATA) __rotcr(_DATA)
#endif
/* ************************************************************************* */
/*  Bit shifting                                                             */
/* ************************************************************************* */
/* TODO: check the usage of this */

#if __RENESAS_PREREQ(9, 4)
# define shll(_DATA) _builtin_shll(_DATA)
# define shlr(_DATA) _builtin_shlr(_DATA)
# define shar(_DATA) _builtin_shar(_DATA)

#elif __GNUC_ASM
static __asm_inline __uint32_t __shll(__uint32_t __data) {
	__asm("shll %0" : "+r"(__data));
	return (__data); }
static __asm_inline __uint32_t __shlr(__uint32_t __data) {
	__asm("shlr %0" : "+r"(__data));
	return (__data); }
static __asm_inline __uint32_t __shar(__uint32_t __data) {
	__asm("shar %0" : "+r"(__data));
	return (__data); }

# define shll(_DATA) __shll(_DATA)
# define shlr(_DATA) __shlr(_DATA)
# define shar(_DATA) __shar(_DATA)
#endif
/* ************************************************************************* */
/*  Clip values                                                              */
/* ************************************************************************* */
/* Return the value if it is in range (-128 to 127 if the destination clip is
 * unsigned byte), the lower limit if it is under it, and the upper limit if it
 * is above it. */

#if !defined(_SH2A) && !defined(_SH2AFPU)
#elif __RENESAS_PREREQ(9, 4)
# define clipsb(_DATA) _builtin_clipsb(_DATA)
# define clipsw(_DATA) _builtin_clipsw(_DATA)
# define clipub(_DATA) _builtin_clipub(_DATA)
# define clipuw(_DATA) _builtin_clipuw(_DATA)

#elif __GNUC_ASM
static __asm_inline __int32_t __clipsb(__int32_t __data) {
	__asm("clips.b %0" : "+r"(__data));
	return (__data); }
static __asm_inline __int32_t __clipsw(__int32_t __data) {
	__asm("clips.w %0" : "+r"(__data));
	return (__data); }
static __asm_inline __int32_t __clipub(__int32_t __data) {
	__asm("clipu.b %0" : "+r"(__data));
	return (__data); }
static __asm_inline __int32_t __clipuw(__int32_t __data) {
	__asm("clipu.w %0" : "+r"(__data));
	return (__data); }

# define clipsb(_DATA) __clipsb(_DATA)
# define clipsw(_DATA) __clipsw(_DATA)
# define clipub(_DATA) __clipub(_DATA)
# define clipuw(_DATA) __clipuw(_DATA)
#endif
/* ************************************************************************* */
/*  TBR interaction                                                          */
/* ************************************************************************* */
/* TODO: what's TBR? */

#if !defined(_SH2A) && !defined(_SH2AFPU)
#elif __RENESAS_PREREQ(9, 4)
# define set_tbr(_DATA) _builtin_set_tbr(_DATA)
# define get_tbr()      _builtin_get_tbr()

#elif __GNUC_ASM
# define set_tbr(_DATA) ((void)0)
# define get_tbr()      ((void)0)
#endif
/* ************************************************************************* */
/*  Bit?                                                                     */
/* ************************************************************************* */
/* TODO: what is this? */

#if __RENESAS_PREREQ(9, 4)
# define bset(_DATA, _OFF) _builtin_bset(_DATA, _OFF)
# define bclr(_DATA, _OFF) _builtin_bclr(_DATA, _OFF)

# define    bcopy(_DATA1, _OFF1, _DATA2, _OFF2) \
	_builtin_bcopy(_DATA1, _OFF1, _DATA2, _OFF2)
# define    bnotcopy(_DATA1, _OFF1, _DATA2, _OFF2) \
	_builtin_bnotcopy(_DATA1, _OFF1, _DATA2, _OFF2)

#elif __GNUC_ASM
# define bset(_DATA, _OFF) ((void)0)
# define bclr(_DATA, _OFF) ((void)0)

# define bcopy(_DATA1, _OFF1, _DATA2, _OFF2)    ((void)0)
# define bnotcopy(_DATA1, _OFF1, _DATA2, _OFF2) ((void)0)
#endif

__END_DECLS